1. Field of the Invention
The present invention relates to the application of selective scrambling to a channel coding circuit, for example, in a digital video tape recorder.
2. Description of the Prior Art
A digital video tape recorder of a type to which the present invention is applicable will be described with reference to FIG. 1 in which a video signal, for example, according to the NTSC system, is supplied to an input terminal 1. The NTSC video signal applied to the input terminal 1 is supplied to an analog-to-digital (A/D) converting circuit 2, in which it is converted to a digital data signal. The digital data signal is supplied to a bit reduction circuit 3, in which it is reduced in bit number and is then fed to an error correction code (ECC) encoder 4. The ECC encoder 4 adds a parity code for error correction and the like to the data signal. The data signal having the parity code added thereto is supplied to a channel coder 5, in which it is converted to a data series whose characteristic conforms to the characteristic of a tape head system of the digital video tape recorder. The data series is supplied to an adding circuit 6, in which it is added to a predetermined synchronizing (SYNC) code from a synchronizing code generating circuit 7 to provide a recording data signal. The recording data signal which includes the synchronizing code is supplied from the adding circuit 6 through a recording amplifier 8 to a recording head 9 and is thereby recorded on a magnetic tape 10
Upon playback, a signal reproduced from the magnetic tape 10 by a reproducing head 11 is supplied through a playback amplifier 12 to an equalizer 13, in which it is waveform-shaped in a predetermined manner. The thus waveform-shaped signal is supplied to a data reproducing circuit 14 which reproduces a data series therefrom. The reproduced data series is supplied to a channel decoder 15 which operates in a manner exactly opposite the operation of the channel coder 5 provided at the recording side. The decoded signal from the channel decoder 15 is supplied to an error correction code (ECC) decoder 16, in which it is error-corrected by the above-mentioned parity code. The error-corrected signal is reduced in bit number by a bit reduction circuit 17 and is then converted from digital to analog form by a digital-to-analog (D/A) converting circuit 18. Finally, the reproduced analog video signal is provided at an output terminal 19.
In the use of the digital video tape recorder of FIG. 1 for recording on a previously recorded tape, a video signal is generally rewritten by a so-called overwrite system. In such overwriting, if an already recorded signal contained a low frequency component, there is then the risk that a satisfactory erasing characteristic will not be achieved in the next overwrite because the low frequency component is recorded in a relatively deep layer of the tape or other magnetic record medium. Further, there is a substantial possibility that a low frequency component in the signal recorded in adjacent tracks will result in a cross-talk component upon playback.
Furthermore, when a rotary transformer is provided for transmitting signals to and from the head or heads of the digital video tape recorder, the low frequency band that can be transmitted by the rotary transformer is limited so that a low frequency component in the recorded signal causes distortion in the waveform of the reproduced signal.
Therefore, the digital video tape recorder according to the prior art includes the channel coder 5 and the channel decoder 15 in order to reduce the low frequency component. FIGS. 2A and 2B illustrate known circuit arrangements that can be used for the channel coder 5 and the channel decoder 15, respectively, in FIG. 1, and which utilize an M series signal as a pseudo-random signal.
In the channel coder 5 shown in FIG. 2A, the signal from the ECC encoder 4 (FIG. 1) is supplied through an input terminal 21 to a modulo (mod.)2-adder 22 which may be constituted by an exclusive-OR gate. A reset signal associated with a predetermined synchronizing block, and which is applied to a terminal 23, is supplied therefrom to an M series generator 24. The M series signal from the M series generator 24 is also supplied to the mod. 2-adder 22 which scrambles the M series signal for effecting the channel coding. The reset signal applied to the terminal 23 is also supplied to the synchronizing code generator 7 which provides the above-mentioned synchronizing code. The synchronizing code is supplied to the adding circuit 6, in which it is added to the data series from the mod. 2-adder 22, and the resulting added output is applied from an output terminal 25 to the recording amplifier 8 shown in FIG. 1.
In the channel decoder 15 shown in FIG. 2B, the data signal from the data reproducing circuit 14 (FIG. 1) is supplied through an input terminal 26 to a mod. 2-adder 27 which is also constituted by an exclusive-OR gate. The signal from the terminal 26 is also supplied to a synchronizing code detecting circuit 28 which detects the above-mentioned synchronizing code. The detected signal is supplied from circuit 28 to an M series generator 29 which provides an M series signal to the mod. 2-adder 27 which effects channel decoding, that is, decodes the signal scrambled by the M series signal in the channel coder 5. The resulting decoded signal is supplied through an output terminal 30 to the ECC decoder 16 (FIG. 1).
The low frequency component in the signal to be recorded is reduced by adding the M series signal to the pseudo-random signal in the modulo 2 adder 22 in FIG. 2A, whereby a recording data signal having a reduced low frequency component is generated. Upon playback the M series signal is added in the mod.2-adder 27 to the same pseudo-random signal as in the recording mode resulting in the original data signal being decoded.
If the M series signal is added to the pseudo-random signal in a modulo 2 adder for effecting the channel coding and the channel decoding as described above, in the absence of any other data signal processing, when a certain relationship is established between the pattern of the recording signal and that of the M series signal, there is the possibility that such relationship will give rise to the occurrence of a low frequency component. The occurrence of the low frequency component is inevitable from a probability standpoint, and it is impossible to escape such inevitability. The occurrence of such low frequency component causes deterioration of the overwrite characteristic, the cross-talk characteristic, the waveform characteristic and the like, as described above.
Further, in a digital magnetic recording and reproducing apparatus, such as, the above described digital video tape recorder, if the digital data series (represented in the binary form of "1" or "0") is directly recorded, the following problems arise:
1. The maximal frequency of a recorded signal is increased to such extent that the recorded signal cannot be read.
2. Direct current and low frequency components frequently appear in the recorded signal so that, when a digital signal is recorded and reproduced by the head system utilizing a rotary transformer, distortion occurs in the reproduced signal. As a result, it is frequently observed that the reproduced information deviates considerably from the recorded information.
3. When digital data is recorded, a data series is generally recorded according to the so-called self-clock system together with a clock component. If many digital "1"' or "0"' appear in succession or contiguously, the error rate in extracting the clock component at the playback side is increased.
In order to solve the above-mentioned problems, it is known to arrange a digital magnetic recording and reproducing apparatus so that, upon recording, a digital input signal is converted to a recording signal having a predetermined frequency characteristic by a channel coding circuit, and this recording signal is recorded on a magnetic record medium by a recording head. Upon playback, a signal reproduced from the magnetic record medium by a playback head is supplied to, and is reproduced by, a decoder whose converting characteristic is opposite to that of the channel coding circuit. Three channel coding systems are known that are each based on a partial response (PR) system which makes effective use of inter-symbol interference in the digital recording. These three channel coding systems will be explained below: